1. Field of the Invention
The present invention relates to a clock-supply control system of digital-signal processors.
2. Description of the Prior Art
FIG. 10 is a block diagram showing the configuration of a conventional digital-signal processing block. Reference numeral 1 shown in the figure is the digital-signal processing block and reference numeral 2 is a data input unit for inputting data 3. Reference numeral 4 is a digital-signal processor, referred to hereafter simply as a DSP, for inputting data 5 from the data input unit 2 and carrying out digital processing on the data 5 in synchronization with a clock signal 6. Reference numeral 7 is a data output unit for inputting data 8 from the DSP 4 and outputting data 9 to a circuit at the next stage. Reference numeral 10 is a frequency multiplier for multiplying the frequency of a system clock signal 11 in order to generate the clock signal 6 for driving the operation of the DSP 4.
Below is description of the operation of the digital-signal processing block.
A digital-signal processing technique using a DSP is known as a conventional method for carrying out digital-signal processing on audio or video data. Examples of such digital-signal processing are MPEG decoding and Dolby digital (AC3) decoding.
FIG. 10 is a diagram showing a digital-signal processing block having an embedded DSP 4 for carrying out such processing. Data 3 supplied to the data input unit 2 is transferred to the DSP 4 as data 5 with appropriate timing. The DSP 4 carries out digital processing on the data 5 in synchronization with the clock signal 6 in accordance with firmware embedded in the DSP 4. The DSP 4 then provides the data output unit 7 with data 8, which has completed the digital processing, with appropriate timing. The data output unit 7 then properly outputs the data 8 to a circuit at the next stage as data 9. It should be noted that the clock signal 6 for driving the operation of the DSP 4 is obtained by multiplying the frequency of the system clock 11 using the frequency multiplier 10.
The frequency of the clock signal 6 must be set at a value between a minimum frequency required for executing desired functions to carry out digital processing on the data 5 and a maximum frequency, above which the DSP 4 will most likely perform a malfunction.
In the case of a digital-signal processing block which is actually implemented by an LSI mounted on a board, the clock signal 6 supplied to the DSP 4 is normally generated from the system clock signal 11 of the board. In this way, oscillating elements can be eliminated and a non-synchronous frequency that can become a noise source can be avoided. It should be noted that the frequencies of the system clock signal used in an audio processing system are 256 fs and 384 fs where 1 fs is equal to 44.1 kHz.
In the case of a clock signal 6 generated from a board system clock 11 as described above, the clock signal 6 supplied to the DSP 4 may be obtained with a frequency which is higher than a minimum frequency required for the operation of the DSP 4 by an unnecessarily large difference. For example, assume that the minimum frequency required for the operation of the DSP 4 is 30 MHz and the system clock signal 11 has a frequency of 256 fs which is equal to 11.25 MHz. Let the frequency of the system clock signal be multiplied by 4 by means of the frequency multiplier 10 to generate a clock signal 6 to be supplied to the DSP 4 with a frequency of 4.times.11.25 MHz=45 MHz. In this case, the difference between the frequency of the clock signal 6 and the minimum frequency required for the operation of the DSP 4 is 45-30 =15 MHz. As a result, unnecessary operations may inadvertently take place even after the required digital processing has been completed early by the DSP 4 due to the clock signal 6 with an excessively high frequency.
The conventional digital-signal processing has a configuration described above wherein the clock signal 6 supplied to the DSP 4 is generated by merely multiplying the frequency of the system clock signal 11 using the frequency multiplier 10. Thus, the clock signal 6 may have a frequency which is higher than a minimum frequency required for the operation of the DSP 4 by an unnecessarily large difference. As a result, unnecessary operations may inadvertently take place even after the required digital processing has been completed early by the DSP 4 due to the clock signal 6 with an excessively high frequency, raising a problem that the amount of power consumed by the digital-signal processor increases unnecessarily.
It should be noted that the prior art is disclosed in, among other documents, JP-A No. 7-129272.